The present invention relates generally to integrated circuits, and more specifically to lowering power consumption in integrated circuits during certain modes of operation.
Many battery-powered portable electronic devices, such as laptop computers, Portable Digital Assistants, digital cameras, cell phones and the like, require memory devices that provide large storage capacity and low power consumption. One type of memory device that is well-suited to use in such portable devices is flash memory, which is a type of semiconductor memory that provides relatively large nonvolatile storage capacity for data. The nonvolatile nature of the storage means that the flash memory does not require power to retain the data, as will be appreciated by those skilled in the art.
A typical flash memory comprises a memory-cell array having an array of memory cells arranged in rows and columns and grouped into blocks. FIG. 1 illustrates a conventional flash memory cell 100 formed by a field effect transistor including a source 102 and drain 104 formed in a substrate 106, with a channel 108 being defined between the source and drain. Each of the memory cells 100 further includes a control gate 110 and a floating gate 112 formed over the channel 108 and isolated from the channel and from each other by isolation layers 114. In the memory-cell array, each memory cell 100 in a given row has its control gate 110 coupled to a corresponding word line WL and each memory cell in a given column has its drain 104 coupled to a corresponding bit line BL. An alternating source AS that switches between ground and an erase voltage is coupled to the source 102. The sources 102 of each memory cell 100 in a given block are coupled together to allow all cells in the block to be simultaneously erased, as will be appreciated by those skilled in the art.
The memory cell 100 is charged or programmed by applying appropriate voltages to the source 102, drain 104, and control gate 110 and thereby injecting electrons exe2x88x92from the drain 104 and channel 108 through the isolation layer 114 and onto the floating gate 112. Similarly, to erase the memory cell 100, appropriate voltages are applied to the source 102, drain 104, and control gate 110 to remove electrons exe2x88x92through the isolation layer 114 to the source 102 and channel 108. The presence or absence of charge on the control gate 112 adjusts a threshold voltage of the memory cell 100 and in this way stores data in the memory cell. When charge is stored on the floating gate 112, the memory cell 100 does not turn ON when an access voltage is applied through the word line WL to the control gate 110, and when no charge is stored on the floating gate the cell turns ON in response to the access voltage. In this way, the memory cell 100 stores data having a first logic state when the cell turns ON and having a second logic state when the cells does not turn ON.
To reduce the power consumption and thereby extend the battery life in portable electronic devices, the flash memory typically operates in a low-power or standby mode when the memory is not being accessed. When a flash memory is operating in the standby mode, the memory will at some point be activated to commence data transfer operations in an active mode of operation. For example, in a portable device the flash memory may be operated in the standby mode when a key has not been pressed for a specified time, and be activated in response to a user pressing a key. The time required to switch from the standby mode to the active mode is ideally minimized so that a user does not experience a delay due to the flash memory changing modes of operation. Thus, the flash memory should be able to begin transferring data to and from the memory cells 100 as soon as possible after termination of the standby mode. In a conventional flash memory, a chip enable signal CE# is applied to the memory and places the memory in the standby and active modes when inactive high and active low, respectively. The xe2x80x9c#xe2x80x9d designates a signal as being active low, as will be appreciated by those skilled in the art.
Certain circuits within the flash memory continue operating during the standby mode to enable the flash memory to more quickly return to the active mode of operation. For example, as illustrated in FIG. 2, a conventional flash memory includes a charge pump 200 that generates a word line drive voltage VX that is used by row drivers 202 in activating corresponding word lines WL. Each row driver 202 is coupled to a respective word line WL1-WLN in the memory-cell array (not shown) and receives a corresponding decoded row address signal DRA1-DRAN. When the received DRA1-DRAN signal indicates the corresponding row of memory cells 100 is to be activated, the row driver 202 applies the voltage VX to the word line WL1-WLN to thereby activate he row of memory cells 100 (not shown in FIG. 2) coupled to the word line. When the received DRA1-DRAN signal indicates the corresponding row of memory cells 100 is to be deactivated, the row driver 202 drives the corresponding word line WL1-WLN to ground to deactivate the row of memory cells 100.
During the standby mode, the charge pump 200 continues generating the word line drive voltage VX so that the row drivers 202 can more quickly activate a selected word line WL when the flash memory is thereafter placed in the active mode. The faster the flash memory can activate a selected word line WL, the faster data can be read from the memory upon return to the active mode, and thus the faster a portable electronic device containing the memory can return to normal operation. As will be understood by those skilled in the art, a bandgap voltage reference 204 generates a bandgap voltage reference VBG that is supplied to the charge pump 200, and the charge pump 200 utilizes the bandgap reference voltage VBG in generating the supply voltage VX, as will be understood by those skilled in the art. The bandgap voltage reference 204 is a popular analog circuit for generating the bandgap reference voltage VBG that is very stable as a function of temperature and as a function of variations in a supply voltage VCC supplied to the bandgap voltage reference. One skilled in the art will understand various circuits that can be utilized in forming the bandgap voltage reference 204, charge pump 200, and row drivers 202, and thus, for the sake of brevity, the details of these components will not be discussed herein. Moreover, although the voltage reference 204 is described as being a bandgap voltage reference, other suitable voltage references may also be utilized, as will be understood by those skilled in the art.
In operation, the conventional bandgap voltage reference 204 consumes a relatively large current in generating the reference voltage VBG. As will be appreciated by those skilled in the art, the bandgap voltage reference 204 draws a relatively large current to enable the voltage reference to quickly charge the reference voltage VBG to its desired value and maintain the reference voltage in response to fluctuations in the supply voltage VCC. As a result, during the standby mode of operation the bandgap voltage reference 204 draws a relatively large current, which increases the power consumption of the flash memory containing the bandgap voltage reference and reduces the battery life of a portable device containing the memory. If a low-current bandgap voltage reference 204 were used, the bandgap reference voltage VBG will not have the required stability as a function of temperature and variations in the supply voltage VCC, and the bandgap voltage reference would take an undesirably long time to charge the voltage VBG to the desired value when the supply voltage VCC is initially supplied to the bandgap voltage reference.
There is a need for reducing the current consumption of a flash memory during a standby mode of operation while still providing a highly stable bandgap reference voltages to required circuits in the memory, and for minimizing the time required for the flash memory to switch from the standby to active mode of operation.
According to one aspect of the present invention, a voltage switching circuit includes an active voltage reference receiving a mode signal and operable responsive to the mode signal going active to generate a first reference voltage. The active voltage reference terminates generation of the first reference voltage responsive to the mode signal going inactive. A standby voltage reference generates a second reference voltage, and a multiplexer coupled to the active and standby voltage references applies the first and second reference voltages on an output responsive to a selection signal going active and inactive, respectively. A delay circuit is coupled to the multiplexer and receives the mode signal. The delay circuit drives the selection signal active a delay time after the mode signal goes active in response to the mode signal going active and drives the selection signal inactive without the delay time responsive to the mode signal going inactive.
According to another aspect of the present invention, a method of operating a memory includes generating a first reference voltage and detecting an active mode of operation of the memory. Upon detection of the active mode, commencing the charging of a node to develop a second reference voltage having a desired value on the node. The word line drive voltage is generated using the first reference voltage while the node is charging the second reference voltage to the desired value. The word line drive voltage is generated using the second reference voltage once the second reference voltage on the node has been charged to the desired value. A standby mode of operation of the memory is detected, and upon detection of the standby mode, the charging of the node is terminated and the word line drive voltage is generated using the first reference voltage.